Mode tunable p-type Si nanowire transistor based zero drive load logic inverter.

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Traditional inverters face limitations in power efficiency and scalability.
• Silicon nanowire transistors offer potential for enhanced device performance.
• Gate dielectric engineering is crucial for controlling transistor behavior.

Purpose of the Study:

• To demonstrate a design platform for a zero drive load logic inverter.
• To utilize p-channel silicon nanowire transistors for inverter fabrication.
• To control transistor operating modes via gate dielectric implantation.

Main Methods:

• Fabrication of a logic inverter using p-channel silicon nanowire transistors.
• Implementation of an implantation process into the gate dielectric layer.
• Characterization of the inverter's performance, including gain and operating voltage.

Main Results:

• Successful demonstration of a design platform for the logic inverter.
• Fabrication of a nanowire-based Class D inverter.
• Achieved a gain value of 4.6 at a supply voltage (V(DD)) of -20 V.

Conclusions:

• The developed design platform enables efficient logic inverter fabrication.
• Silicon nanowire transistors are viable for high-gain inverter applications.
• Gate dielectric implantation is an effective method for controlling transistor modes.