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Low-temperature poly-Si nanowire junctionless devices with gate-all-around TiN/Al2O3 stack structure using an
Nanoscale Research Letters
|June 26, 2012
Summary
This study introduces a novel gate-all-around (GAA) silicon nanowire (NW) junctionless transistor. The device utilizes a low-temperature fabrication process and TiN/Al contacts for improved performance.
Area of Science:
- Materials Science
- Electrical Engineering
- Nanotechnology
Background:
- Traditional silicon transistors face scaling limitations.
- Gate-all-around (GAA) architectures offer improved electrostatic control.
- Low-temperature poly-Si nanowire (NW) fabrication presents a pathway for cost-effective device manufacturing.
Purpose of the Study:
- To develop and characterize a novel gate-all-around (GAA) low-temperature poly-Si nanowire (NW) junctionless transistor.
- To investigate the electrical properties of the fabricated device using TiN/Al contacts.
Main Methods:
- Fabrication of gate-all-around (GAA) silicon nanowire (NW) structures using a low-temperature process.
- Formation of junctionless transistors with TiN/Al gate and source/drain contacts.
- Electrical characterization including I-V measurements and performance analysis.
Main Results:
- Successful fabrication of functional GAA low-temperature poly-Si NW junctionless devices.
- Demonstration of transistor operation with TiN/Al contacts.
- Analysis of device performance metrics, highlighting potential advantages.
Conclusions:
- The developed GAA low-temperature poly-Si NW junctionless device with TiN/Al contacts is a promising candidate for future electronic applications.
- This work demonstrates the feasibility of integrating GAA architecture with low-temperature fabrication for advanced semiconductor devices.
