Chemical-mechanical planarization aided dimple etching for self alignment.

Area of Science:

• Materials Science
• Electrical Engineering
• Semiconductor Manufacturing

Background:

• Through silicon via (TSV) technology is crucial for 3D integrated circuits (3D ICs).
• Copper Chemical-mechanical planarization (CMP) is essential for achieving planar surfaces in TSV fabrication, requiring high removal rates and low dishing.
• Current alignment methods face challenges in achieving precision for advanced 3D ICs.

Purpose of the Study:

• To develop a new self-alignment method for TSV Cu using dimples on the back surface.
• To investigate the potential of a bump-dimple structure for self-alignment applications.
• To optimize Chemical-mechanical planarization (CMP) aided dimple etching for deep and uniform dimple formation.

Main Methods:

• Development of a self-alignment method utilizing dimples on the TSV Copper back surface.
• Application testing of a bump-dimple structure using a solder ball array pretest tool.
• Detailed study of Chemical-mechanical planarization (CMP) aided dimple etching for precise dimple creation.

Main Results:

• CMP effectively creates clean oxide surfaces and clear dishing on Cu TSVs, serving as an etching seed.
• Achieved uniform dimple depths ranging from 7 to 9 micrometers.
• Demonstrated consistent dimple formation across varying via diameters (10 to 50 micrometers) with short etching times (15 seconds).

Conclusions:

• The developed CMP-aided dimple etching process is highly effective for creating uniform dimples in TSV Cu.
• The dimple-based self-alignment method shows significant potential for improving 3D IC manufacturing precision.
• This technique offers a robust solution for deep and uniform dimple formation, crucial for advanced semiconductor packaging.