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Published on: May 13, 2020
HfOx-based vertical resistive switching random access memory suitable for bit-cost-effective three-dimensional
Shimeng Yu1, Hong-Yu Chen, Bin Gao
1Department of Electrical Engineering and Center for Integrated Systems, Stanford University, California 94305, United States. simonyu@stanford.edu
This study demonstrates a cost-effective 3D vertical resistive switching random access memory (RRAM) using HfOx. The novel architecture achieves high performance for future ultra-high-density nonvolatile memory applications.
Area of Science:
- Materials Science
- Electrical Engineering
- Computer Engineering
Background:
- Three-dimensional (3D) cross-point array architecture is crucial for ultra-high-density nonvolatile memory.
- Reducing manufacturing costs is essential for widespread adoption of 3D memory technologies.
Purpose of the Study:
- To demonstrate a bit-cost-effective technology path for 3D integration of memory devices.
- To fabricate and characterize a double-layer HfOx-based vertical resistive switching random access memory (RRAM).
Main Methods:
- Fabrication of a vertical RRAM structure using atomic layer deposition of HfOx on trench sidewalls.
- Engineering of electrode/oxide interfaces with a TiON layer to achieve nonlinear current-voltage (I-V) characteristics.
- Characterization of device performance including switching speed, endurance, and data retention.
Main Results:
- Successful fabrication of HfOx vertical RRAM with a single critical lithography step.
- Achieved selectorless operation due to nonlinear I-V characteristics.
- Demonstrated excellent performance: reset current <50 μA, switching speed <100 ns, endurance >10^8 cycles, read disturbance immunity >10^9 cycles, and data retention >10^5 s at 125 °C.
Conclusions:
- The developed HfOx vertical RRAM offers a promising solution for cost-effective ultra-high-density nonvolatile memory.
- The integration of TiON interfacial layers enables selectorless operation, simplifying array design.
- The excellent performance metrics indicate the viability of this technology for next-generation memory applications.
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