A neuromorphic VLSI design for spike timing and rate based synaptic plasticity

Area of Science:

• Neuromorphic Engineering
• Computational Neuroscience
• VLSI Design

Background:

• Triplet-based Spike Timing Dependent Plasticity (TSTDP) offers advanced synaptic plasticity beyond conventional pair-based STDP (PSTDP).
• TSTDP can replicate biological experimental outcomes where PSTDP fails.
• The Bienenstock-Cooper-Munro (BCM) rule's behavior can emerge from TSTDP.

Purpose of the Study:

• To propose and design an analogue VLSI circuit implementation of the TSTDP rule.
• To demonstrate the circuit's ability to adjust synaptic weights based on spike timing differences.
• To investigate the emergence of a BCM-like learning rule from the TSTDP circuit.

Main Methods:

• Design of an analogue TSTDP circuit using AMS 0.35 μm CMOS process.
• Simulation using Synopsys and Cadence design kits.
• 1000-run Monte Carlo (MC) analysis to assess performance under process variations.

Main Results:

• The circuit successfully alters synaptic weights according to spike timing patterns.
• The TSTDP circuit exhibits BCM-like learning behavior.
• MC analysis indicates process variations can be mitigated, but variation-aware design is crucial for large-scale networks.

Conclusions:

• The proposed analogue TSTDP circuit is a viable approach for neuromorphic learning systems.
• The design shows promise for future VLSI implementations of both spike timing and rate-based learning.
• Further design techniques are needed to ensure high performance in large-scale neural networks.