Memristor-based programmable logic array (PLA) and analysis as Memristive networks

Area of Science:

• Electronics
• Nanotechnology
• Computer Engineering

Background:

• The memristor, theorized by Chua in 1971, is a two-terminal device whose resistance depends on charge flow history.
• Memristor cross-bar architectures offer high integration density, improved performance, and reduced power dissipation for System-on-Chip (SoC) designs.
• Current memristor cross-bar approaches face challenges like lack of voltage gain and sneak current paths.

Purpose of the Study:

• To propose a novel Memristor-based programmable logic array (PLA) architecture.
• To develop an analytical model for analyzing logic levels in memristive networks.
• To address the limitations of existing memristor cross-bar circuit configurations.

Main Methods:

• A new Memristor-based programmable logic array (PLA) architecture is designed.
• An analytical model is developed to evaluate logic levels within memristive networks.
• The proposed architecture supports up to 12 inputs and can be cascaded for more variables.

Main Results:

• The proposed PLA architecture effectively utilizes memristors' switching capabilities between high and low resistance states.
• The analytical model provides insights into logic level behavior in memristive networks.
• The architecture demonstrates feasibility with memristors exhibiting an R(off)/R(on) ratio between 55 and 160.

Conclusions:

• The proposed Memristor-based PLA architecture presents a viable solution for advanced SoC implementations.
• The developed analytical model aids in understanding and optimizing memristive logic networks.
• This research contributes to overcoming existing challenges in memristor-based circuit design, paving the way for future electronic innovations.