Design of a reversible single precision floating point subtractor.

Area of Science:

• Digital circuit design
• Low-power electronics
• Reversible computing

Background:

• Reversible logic minimizes power dissipation, essential for low-power digital circuits.
• Floating-point operations are fundamental in computing, with subtraction being highly frequent.
• Existing research lacks efficient reversible floating-point subtractors.

Purpose of the Study:

• To propose an efficient reversible single-precision floating-point subtractor.
• To develop optimized reversible modules for comparator, subtractor, and normalization units.
• To enhance designs for low-power digital circuit applications.

Main Methods:

• Designed reversible 8-bit and 24-bit comparator and subtractor units.
• Implemented a 24-bit reversible leading zero detector and shift register for normalization.
• Proposed two new 3x3 reversible gates for an optimized 1-bit reversible comparator.
• Analyzed designs based on reversible gates, garbage outputs, constant inputs, and quantum costs.

Main Results:

• Developed an efficient reversible single-precision floating-point subtractor.
• The proposed reversible 1-bit comparator shows improvements in gate count, transistor count, and garbage outputs.
• Simulations and synthesis were performed using Modelsim and Xilinx Virtex5.
• The 32-bit reversible floating-point subtractor achieved a low on-chip power consumption of 0.410 W.

Conclusions:

• The proposed design offers an efficient solution for reversible floating-point subtraction.
• The optimized reversible modules contribute to reduced power dissipation in digital circuits.
• This work advances the field of reversible logic for practical low-power computing applications.