An 81.6 μW FastICA processor for epileptic seizure detection

Area of Science:

• Biomedical Engineering
• Signal Processing
• Integrated Circuit Design

Background:

• Epileptic seizure detection requires accurate signal processing from multi-channel data.
• Independent Component Analysis (ICA) is effective for separating artifacts from neural signals.
• Existing ICA algorithms face challenges in energy efficiency and hardware implementation.

Purpose of the Study:

• To develop an area- and power-efficient hardware processor for epileptic seizure detection.
• To accelerate the computation of Independent Component Analysis (ICA) using FastICA algorithm.
• To reduce energy dissipation in the signal processing pipeline.

Main Methods:

• Applied FastICA algorithm for signal separation in multi-channel electroencephalogram (EEG) data.
• Utilized eigenvalue decomposition (EVD) with an approximate Jacobi algorithm for preprocessing.
• Implemented a fixed-point architecture with optimized memory elements and reduced wordlength.

Main Results:

• Achieved a 77.2% area reduction in EVD architecture and significant power/area savings in memory.
• The fabricated 90 nm CMOS chip has a core area of 0.40 mm² and dissipates 81.6 μW.
• Demonstrated a computation delay of 84.2 ms per frame, achieving 3.4x speedup over prior work.

Conclusions:

• The developed FastICA processor offers substantial improvements in power efficiency and silicon area.
• The hardware implementation meets latency constraints for real-time epileptic seizure detection.
• Verified performance on human datasets, demonstrating its clinical applicability.