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Updated: Apr 25, 2026

Fabrication of Gate-tunable Graphene Devices for Scanning Tunneling Microscopy Studies with Coulomb Impurities
Published on: July 24, 2015
Extrinsic and intrinsic charge trapping at the graphene/ferroelectric interface
M Humed Yusuf1, Bent Nielsen, M Dawber
1Department of Physics and Astronomy, Stony Brook University , Stony Brook, New York 11794, United States.
Abstract:
The interface between graphene and the ferroelectric superlattice PbTiO3/SrTiO3 (PTO/STO) is studied. Tuning the transition temperature through the PTO/STO volume fraction minimizes the adorbates at the graphene/ferroelectric interface, allowing robust ferroelectric hysteresis to be demonstrated. "Intrinsic" charge traps from the ferroelectric surface defects can adversely affect the graphene channel hysteresis and can be controlled by careful sample processing, enabling systematic study of the charge trapping mechanism.
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