Advanced Cu chemical displacement technique for SiO2-based electrochemical metallization ReRAM application

Area of Science:

• Materials Science
• Electrical Engineering
• Nanotechnology

Background:

• Resistive random-access memory (ReRAM) is a promising non-volatile memory technology.
• Fabrication of high-performance ReRAM requires precise control over material interfaces and layer thicknesses.
• Existing copper deposition methods face challenges in controlling these critical parameters for advanced device structures.

Purpose of the Study:

• To investigate an advanced copper (Cu) chemical displacement technique (CDT) for fabricating Cu/SiO2-stacked ReRAM.
• To explore the impact of varying chemical displacement time on ReRAM performance.
• To demonstrate the advantages of CDT for 1-transistor-1-ReRAM (1T-1R) and system-on-chip integration.

Main Methods:

• Fabrication of Cu/SiO2-stacked ReRAM using a CDT with varied displacement times.
• Characterization of the Cu-SiO2 interface and SiO2 layer thickness using scanning electron microscopy (SEM) and atomic force microscopy (AFM).
• Electrical characterization of ReRAM devices, including operation voltages, data retention, forming/set voltages, on-state current, reset voltage, and endurance.

Main Results:

• CDT allows easy control over the Cu-insulator interface, switching layer thickness, and Cu etching immunity.
• CDT-fabricated ReRAM exhibited lower operation voltages and more stable data retention compared to control samples.
• Increasing Cu CDT processing time decreased forming and set voltages; decreasing time reduced on-state current and reset voltage while improving endurance.

Conclusions:

• The copper chemical displacement technique (CDT) effectively fabricates high-performance Cu/SiO2-stacked ReRAM.
• Switching characteristics of ReRAM devices can be readily modulated by controlling the Cu CDT processing time.
• CDT offers a viable method for integrating advanced ReRAM devices, particularly electrochemical metallization (ECM)-type ReRAM, into 1T-1R structures and system-on-chip designs.