Low power adder based auditory filter architecture.

Area of Science:

• Electrical Engineering
• Biomedical Engineering
• Signal Processing

Background:

• Cochlear devices require long battery life, necessitating low-power components.
• Auditory filters are crucial for processing frequency-variant signals to identify speech.
• Existing filter designs may not meet stringent power consumption requirements.

Purpose of the Study:

• To implement a multiplierless lookup table (LUT) based auditory filter for cochlear devices.
• To reduce power consumption in cochlear implant signal processing.
• To enhance the performance and working life of cochlear implants.

Main Methods:

• Developed and modeled a multiplierless LUT-based auditory filter using Verilog HDL.
• Utilized power-aware adder architectures for output sample summation.
• Simulated the design using Mentor Graphics Model-Sim and synthesized it with Synopsys Design Compiler.
• Mapped the design to a TSMC 65nm technological node and performed power analysis using standard ASIC methodology.

Main Results:

• The proposed FIR filter architecture achieved a 15% reduction in leakage power.
• The design demonstrated a 2.76% increase in performance.
• The multiplierless LUT approach proved effective for low-power auditory filtering.

Conclusions:

• The implemented multiplierless LUT-based auditory filter offers significant power savings for cochlear devices.
• This design contributes to extending the operational lifespan of cochlear implants.
• The optimized filter architecture enhances both power efficiency and performance in auditory signal processing.