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Development and Functionalization of Electrolyte-Gated Graphene Field-Effect Transistor for Biomarker Detection
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Scaling of graphene integrated circuits
Massimiliano Bianchi1, Erica Guerriero, Marco Fiocco
1L-NESS, Department of Physics, Politecnico di Milano, Polo di Como, Via Anzani 42, 22100 Como, Italy. roman.sordan@polimi.it.
Nanoscale
|April 16, 2015
Summary
Researchers explored graphene integrated circuit (IC) scaling, achieving a 31 ps gate delay. This advancement in graphene electronics demonstrates high-frequency potential for future applications.
Area of Science:
- Solid State Physics
- Materials Science
- Electrical Engineering
Background:
- Transistor scaling is crucial for integrated circuit (IC) performance.
- Graphene electronics research has primarily focused on individual transistors, not multi-stage ICs.
Purpose of the Study:
- To investigate the impact of scaling on graphene-based multi-stage ICs.
- To determine the performance limits of scaled graphene ICs.
Main Methods:
- Studied graphene ICs with gate lengths from 3.3 to 0.5 μm.
- Varied channel widths, access lengths, and lead thicknesses.
- Derived the fundamental Johnson limit for scaled graphene ICs.
Main Results:
- Achieved a shortest gate delay of 31 ps per stage in sub-micron graphene ring oscillators (ROs).
- Reached an oscillation frequency of 4.3 GHz, the highest for strictly low-dimensional materials.
- Demonstrated potential for high-frequency applications with small voltage swings.
Conclusions:
- Scaled graphene ICs exhibit significant performance improvements.
- Graphene technology shows promise for high-frequency electronic applications.
- Further scaling can unlock advanced functionalities in graphene-based ICs.
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