An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

Area of Science:

• Neuroscience
• Electrical Engineering
• Computer Engineering

Background:

• Online spike sorting is crucial for real-time neural signal processing.
• Existing methods often face challenges with power consumption and hardware area.

Purpose of the Study:

• To present a novel VLSI architecture for multi-channel online spike sorting.
• To reduce power consumption and hardware area costs in spike sorting circuits.

Main Methods:

• Spike detection using the nonlinear energy operator (NEO).
• Feature extraction employing the generalized Hebbian algorithm (GHA).
• Shared core architecture for spike detection and feature extraction across channels.
• Dedicated channel buffers and a clock gating system to minimize power usage.

Main Results:

• The proposed architecture was implemented using a 90-nm ASIC.
• Demonstrated lower power consumption compared to existing methods.
• Achieved reduced hardware area costs for real-time applications.

Conclusions:

• The novel VLSI architecture offers an efficient solution for multi-channel online spike sorting.
• The design effectively lowers power and area overhead, making it suitable for real-time neural data analysis.