Structural Optimizations of Silicon Based NMOSFETs with a Sunken STI Pattern by Using a Robust Stress Simulation...

Area of Science:

• Semiconductor device physics
• Materials science
• Nanotechnology

Background:

• Scaling metal-oxide-semiconductor field-effect transistors (MOSFETs) below 22 nm necessitates advanced isolation techniques.
• Shallow trench isolation (STI) is critical for device isolation and enhancing carrier mobility in advanced transistors.
• Understanding the impact of STI structures on silicon channel stress is vital for performance optimization.

Purpose of the Study:

• To analyze key design factors of n-type MOSFETs (NMOSFETs) influenced by STI structures and contact etching stop layers.
• To investigate the effect of STI recess depth on silicon channel stress and carrier mobility.
• To present a response surface model for carrier mobility considering sunken STI and source/drain lengths.

Main Methods:

• Finite element method (FEM)-based simulations were employed to analyze silicon channel stress.
• Design of Experiments (DOE) was integrated with simulations to systematically evaluate design factors.
• Factorial designs and response surface methodology were utilized for performance analysis.

Main Results:

• NMOSFETs incorporating a 15 nm deep sunken STI demonstrated approximately 5% greater mobility compared to those with regular STI.
• Simulation-based factorial designs identified STI recess depth as a critical factor affecting device performance.
• A response surface curve was developed to illustrate carrier mobility based on sunken STI and source/drain lengths.

Conclusions:

• Sunken STI designs offer a significant advantage for enhancing NMOSFET carrier mobility.
• STI recess depth is a paramount design parameter for optimizing NMOSFET performance.
• The developed response surface model provides a valuable tool for predicting and optimizing NMOSFET carrier mobility.