Development of Gated Pinned Avalanche Photodiode Pixels for High-Speed Low-Light Imaging

Area of Science:

• Photonics and Semiconductor Devices
• Image Sensor Technology
• High-Speed Imaging Systems

Background:

• Linear-mode avalanche photodiodes (APDs) are explored for high-speed CMOS imaging.
• Comparison with existing literature approaches and Geiger-mode APDs for single-photon counting is presented.

Purpose of the Study:

• To investigate the benefits of linear-mode APDs in high-speed CMOS imaging.
• To analyze APDs biased below breakdown voltage for single-photon counting.
• To present the gated pinned avalanche photodiode pixel concept and initial experimental results.

Main Methods:

• Experimental testing of an 8 × 16 pixel test array based on the gated pinned avalanche photodiode concept.
• Photon-transfer measurements to extract readout noise, full well capacity, and conversion gain.
• Characterization of avalanche junction gain on separate test diodes.

Main Results:

• The sensor demonstrated wavelength-dependent gain under frontside illumination with -32 V substrate bias.
• Readout characteristics showed no dependence on high-voltage bias.
• Key performance metrics include 15 e- rms readout noise, 8000 e- full well capacity, and 75 µV/e- conversion gain.
• A multiplication factor of 1.6 for red light was observed.

Conclusions:

• The gated pinned avalanche photodiode pixel concept shows potential as an alternative to Geiger-mode APDs.
• Further development is needed to demonstrate full feasibility, but initial data is informative.
• The technology is compatible with standard 130 nm CMOS processes.