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Two-terminal floating-gate memory with van der Waals heterostructures for ultrahigh on/off ratio
Quoc An Vu1,2, Yong Seon Shin3, Young Rae Kim3
1Center for Integrated Nanostructure Physics, Institute for Basic Science (IBS), Suwon 16419, Republic of Korea.
Abstract:
Concepts of non-volatile memory to replace conventional flash memory have suffered from low material reliability and high off-state current, and the use of a thick, rigid blocking oxide layer in flash memory further restricts vertical scale-up. Here, we report a two-terminal floating gate memory, tunnelling random access memory fabricated by a monolayer MoS2/h-BN/monolayer graphene vertical stack. Our device uses a two-terminal electrode for current flow in the MoS2 channel and simultaneously for charging and discharging the graphene floating gate through the h-BN tunnelling barrier. By effective charge tunnelling through crystalline h-BN layer and storing charges in graphene layer, our memory device demonstrates an ultimately low off-state current of 10(-14) A, leading to ultrahigh on/off ratio over 10(9), about ∼10(3) times higher than other two-terminal memories. Furthermore, the absence of thick, rigid blocking oxides enables high stretchability (>19%) which is useful for soft electronics.
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