Related Experiment Video
Updated: Feb 27, 2026
06:25
Time Multiplexing Super Resolving Technique for Imaging from a Moving Platform
Published on: February 12, 2014
8.9K
A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate
Chen Yang1, Bingyi Li2, Liang Chen3
1Beijing Key Laboratory of Embedded Real-time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China. yangchen@bit.edu.cn.
Sensors (Basel, Switzerland)
|July 5, 2017
Summary
This study introduces a partial fixed-point processing scheme for onboard Synthetic Aperture Radar (SAR) imaging, significantly reducing power consumption. The developed system achieves high-resolution imaging with reduced hardware costs and power usage for disaster response.
Area of Science:
- Satellite remote sensing
- VLSI circuit design
- Signal processing
Background:
- Onboard real-time Synthetic Aperture Radar (SAR) imaging systems are crucial for rapid disaster response.
- Severe constraints on size, weight, and power (SWaP) challenge high-performance onboard SAR processing.
- The chirp scaling (CS) algorithm presents significant computational demands for real-time SAR imaging.
Purpose of the Study:
- To analyze the computational burden of the chirp scaling (CS) SAR imaging algorithm.
- To propose a partial fixed-point processing scheme to reduce hardware costs and power consumption.
- To verify the fidelity and accuracy of the proposed processing scheme against conventional methods.
Main Methods:
- Analysis of the computational load in the CS SAR imaging algorithm.
- Implementation of a partial fixed-point processing scheme, with Fast Fourier Transform (FFT) in fixed-point and other operations in single-precision floating-point.
- Development of a fixed-point processing error propagation model to determine word length.
- Design and realization of a Field-Programmable Gate Array-Application-Specific Integrated Circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture.
Main Results:
- A customized fixed-point FFT co-processor was implemented using 130 nm CMOS technology.
- The system achieved real-time focusing of SAR raw data (16,384 × 16,384 granularity) with 5-m resolution and 50-km swath width.
- The processing board requires 12 seconds and consumes 21 W, demonstrating significant power efficiency.
Conclusions:
- The proposed partial fixed-point processing scheme effectively reduces computational burden and power consumption for onboard SAR imaging.
- The developed FPGA-ASIC architecture validates the feasibility and performance of the fixed-point processing approach.
- This technology enables high-performance, low-power SAR systems for timely disaster monitoring and response.
