Sub-10 Nanometer Feature Size in Silicon Using Thermal Scanning Probe Lithography.
Yu Kyoung Ryu Cho1, Colin D Rawlings1,2, Heiko Wolf1
1IBM Research Zurich , Säumerstrasse 4, 8803 Rüschlikon, Switzerland.
ACS Nano
|October 31, 2017
Summary
Thermal scanning probe lithography (t-SPL) achieved 11 nm half-pitch lines in a transfer layer and 14 nm half-pitch lines in silicon. Reliable pattern transfer requires >3 nm depth and slightly elevated walls for high-resolution lithography.
Area of Science:
- Nanotechnology
- Materials Science
- Surface Science
Background:
- High-resolution lithography demands precise pattern characterization, especially with thin resist layers.
- Demonstrating successful pattern transfer is crucial for validating device fabrication readiness.
- Thermal scanning probe lithography (t-SPL) offers high resolution, particularly with shallow patterns.
Purpose of the Study:
- Investigate the reliability and resolution limits of t-SPL.
- Determine the optimal applied temperature and force for pattern transfer.
- Establish a benchmark for reliable pattern transfer geometry.
Main Methods:
- Studied pattern transfer reliability as a function of applied temperature and force.
- Utilized a minimum pattern depth of 3 nm and slightly elevated walls as a transfer benchmark.
- Analyzed the formation of 10-20 nm half-pitch dense lines under varying t-SPL conditions.
Main Results:
- Achieved reliable pattern transfer with >3 nm depth and slightly elevated walls.
- Optimized t-SPL conditions yielded 11 nm half-pitch dense lines in HM8006 transfer layer.
- Attained 14 nm half-pitch dense lines and L-lines in silicon with 2.6 nm line edge roughness (3σ).
Conclusions:
- Optimal pattern geometry achieved at ~600 °C, balancing plastic deformation and evaporation.
- Plastic deformation at tight pitches limits pattern depth and achievable resolution.
- Demonstrated high-resolution patterning capabilities of t-SPL in both transfer layers and silicon.
