Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias

Area of Science:

• Semiconductor device physics
• CMOS image sensor technology
• Photon detection

Background:

• Traditional pinned photodiode (PPD) CMOS image sensors face limitations in full depletion and parasitic reverse currents.
• Achieving high quantum efficiency, especially at longer wavelengths, remains a key challenge in image sensor development.

Purpose of the Study:

• To develop and characterize a new PPD CMOS image sensor capable of full depletion with suppressed parasitic reverse currents.
• To evaluate the performance of the new sensor design, focusing on quantum efficiency and operational characteristics.

Main Methods:

• Development of a PPD CMOS image sensor utilizing an additional deep implantation step for parasitic current suppression.
• Fabrication of front-side illuminated (FSI) and back-side illuminated (BSI) prototypes on epitaxial silicon wafers using a 180 nm PPD process.
• Characterization of pixel arrays (10 µm and 5.4 µm) with varying implant parameters, comparing against device simulations.

Main Results:

• The new PPD pixels can be reverse-biased beyond full depletion without significant parasitic leakage currents.
• Optical response of the modified pixels is nearly identical to reference pixels, with excessive charge sharing not being a limiting factor.
• Characterization results align well with device simulations for various pixel configurations.

Conclusions:

• The developed PPD CMOS image sensor successfully suppresses parasitic reverse currents and achieves full depletion.
• This technology enables monolithic PPD CIS with large depleted thickness, promising high quantum efficiency in near-infrared and soft X-ray detection.
• The new design offers a pathway for improved performance in specialized imaging applications.