A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous...

Area of Science:

• Neuromorphic Engineering
• Computer Architecture
• Artificial Intelligence

Background:

• Neuromorphic computing systems utilize event-driven communication for enhanced bandwidth and power efficiency.
• Managing asynchronous event traffic in large-scale neuromorphic systems presents significant challenges in circuit complexity and memory usage.

Purpose of the Study:

• To present a novel routing methodology for neuromorphic systems that addresses challenges in traffic management.
• To minimize memory requirements and latency while maximizing programming flexibility for diverse event-based neural network architectures.

Main Methods:

• Developed a hybrid hierarchical and mesh routing strategy combined with heterogeneous memory structures.
• Implemented the scheme in a prototype multicore neuromorphic processor chip with hybrid analog/digital circuits.
• Validated the approach through theoretical analysis, circuit description, and prototype chip characterization.

Main Results:

• The proposed routing scheme effectively minimizes memory requirements and latency in neuromorphic systems.
• The prototype chip demonstrated successful real-time classification of visual symbols using a convolutional neural network.
• The system supports a wide range of event-based neural network architectures via parameter configuration.

Conclusions:

• The novel routing methodology offers a scalable and efficient solution for managing asynchronous event traffic in neuromorphic computing.
• The developed prototype chip validates the effectiveness of the proposed scheme for advanced AI applications.
• This work advances the development of practical, high-performance neuromorphic processors.