An On-Chip Learning Neuromorphic Autoencoder With Current-Mode Transposable Memory Read and Virtual Lookup Table.

Area of Science:

• Neuromorphic Engineering
• Artificial Intelligence
• VLSI Design

Background:

• Neuromorphic computing aims to mimic the human brain's structure and function.
• On-chip learning is crucial for developing autonomous and adaptive intelligent systems.
• Spiking neural networks (SNNs) offer a biologically plausible and energy-efficient computational model.

Purpose of the Study:

• To present an integrated circuit (IC) implementation of an on-chip learning neuromorphic autoencoder unit.
• To utilize a rate-based spiking neural network architecture for unsupervised learning.
• To achieve efficient processing of multiplications and accumulations for neural network operations.

Main Methods:

• Developed a current-mode signaling scheme with a 500 × 500 6b SRAM-based memory.
• Implemented a transposable memory read for forward and backward propagations.
• Incorporated a virtual lookup table for unsupervised learning of a restricted Boltzmann machine.
• Fabricated the IC using a 28-nm CMOS process.

Main Results:

• Verified the IC in a three-layer encoder-decoder network for image training and recovery.
• Achieved a normalized root mean square error of 0.078 with a dataset of 50 digits.
• Measured energy efficiencies of 4.46 pJ/synaptic operation for inference and 19.26 pJ/synaptic weight update for learning.
• Simulated potential for batch training on 60,000 MNIST datasets.

Conclusions:

• The proposed IC effectively implements on-chip learning for neuromorphic autoencoders.
• The architecture demonstrates high performance and energy efficiency for unsupervised learning tasks.
• The design shows promise for scaling to larger datasets like MNIST.