Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

Area of Science:

• Materials Science
• Electronics Engineering
• Display Technology

Background:

• Amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) face challenges in industrial display backplane production.
• Existing back-channel-etched (BCE) structures exhibit limitations in uniformity and stability for large-area applications.

Purpose of the Study:

• To develop a novel clean etch-stopper (CL-ES) process for fabricating a-IGZO TFTs.
• To enhance the uniformity, reproducibility, and stability of a-IGZO TFTs on large glass substrates (8.5th generation).
• To assess the economic feasibility of transitioning from silicon-based to metal oxide semiconductor-based TFT processes for LCDs.

Main Methods:

• Introduction of a new ~100 nm ES nano-layer in the CL-ES process.
• Simultaneous etching of the 30 nm a-IGZO nano-layer and source-drain electrode layer.
• Fabrication of a-IGZO TFT devices with CL-ES structure on 2200 mm × 2500 mm glass substrates.
• Reliability testing including negative bias temperature illumination stress and positive bias thermal stress (+/-30 V for 3600 s).

Main Results:

• Achieved saturation electron mobility of 8.05 cm²/V·s and Vth uniformity of 0.72 V for CL-ES structured a-IGZO TFTs.
• Significantly reduced threshold voltage (Vth) shifts under stress conditions: -0.51 V (NBTI) and +1.94 V (PBTI) for CL-ES devices.
• Demonstrated substantially lower Vth shifts compared to BCE-structured devices (-3.88 V and +5.58 V).

Conclusions:

• The CL-ES process effectively overcomes technological and economic hurdles for industrial a-IGZO TFT production.
• The improved uniformity and stability of CL-ES a-IGZO TFTs are suitable for large-area display applications.
• The electrical performance indicates a feasible and economic transfer to metal oxide semiconductor-based processes for LCD fabrication.