A high-linearity time-to-digital converter based on dynamically delay-adjustable looped carry chains on FPGAs

Time-to-digital converters (TDCs) act as the core component in many scientific and engineering systems which are based on high-accuracy time measurement. Traditionally, field programmable gate array (FPGA) based TDCs are constructed by organizing carry chains in the tapped delay line style, though acquiring high resolution, the differential nonlinearity (DNL) error is high in the range of 2 least significant bits (LSBs)-4 LSBs. Additionally, their long used length of the carry chain costs rather high resource, which is not friendly for multi-channel TDCs. This paper proposes a new TDC architecture based on dynamically delay-adjustable looped carry chains, which works in the Vernier mode. The TDC contains two looped carry chains, and their oscillation period difference (resolution) is dynamically adjusted by a personal computer program without manual intervene and re-compilation of the TDC circuit. A prototype TDC implemented on a Stratix III FPGA obtains the resolution of 26 ps and the DNL less than 1 LSB, but it only uses two carry chains of length of 32 each. The proposed TDC architecture opens a new way to exploit the capability of the carry chains on FPGAs for high-performance TDC applications.