Vertical-Tunnel Field-Effect Transistor Based on a Silicon-MoS₂ Three-Dimensional-Two-Dimensional Heterostructure.

Area of Science:

• Semiconductor Physics
• Materials Science
• Nanotechnology

Background:

• Tunneling field-effect transistors (TFETs) offer potential for low-power electronics due to their steeper switching characteristics compared to conventional MOSFETs.
• Molybdenum disulfide (MoS₂), a 2D material, has shown promise for TFETs due to its tunable bandgap and high carrier mobility.
• Vertical heterostructures enable compact device designs and potentially enhanced performance by optimizing carrier transport.

Purpose of the Study:

• To design and fabricate a vertical tunneling field-effect transistor (TFET) utilizing a heterostructure of p-doped silicon and n-type molybdenum disulfide (MoS₂).
• To investigate the device's electrical characteristics, including its operating modes, subthreshold swing, on/off current ratio, and ambipolar behavior.
• To analyze the dominant charge transport mechanisms, specifically band-to-band tunneling (BTBT) and trap-assisted tunneling (TAT), at low temperatures.

Main Methods:

• Fabrication of a vertical heterostructure device comprising highly p-doped silicon and n-type MoS₂.
• Electrical characterization of the device across various bias conditions to determine its functional modes and performance metrics.
• Low-temperature measurements to elucidate the contributions of different tunneling mechanisms to the drain current.

Main Results:

• The fabricated p-n heterojunction exhibited a staggered band alignment, enhancing band-to-band tunneling (BTBT) probability.
• The device operated effectively in both tunneling transistor and conventional transistor modes, demonstrating excellent performance.
• Key performance metrics included a minimum subthreshold swing of 15 mV/dec, an average of 77 mV/dec, a high on/off current ratio of ~10⁷ at 1 V, and fully suppressed ambipolar behavior.
• Low-temperature measurements confirmed the contributions of both BTBT and trap-assisted tunneling (TAT) to the drain current, with traps likely originating from interfacial oxide defects.

Conclusions:

• The developed silicon/MoS₂ vertical heterostructure TFET shows significant potential for low-power electronic applications.
• The device's performance is attributed to the favorable staggered band alignment and efficient tunneling mechanisms.
• Understanding the role of interfacial defects and trap-assisted tunneling is crucial for further optimization and reliability of such devices.