Four-Wire Interface ASIC for a Multi-Implant Link.

Area of Science:

• Biomedical Engineering
• Implantable Devices
• Integrated Circuits

Background:

• Active implantable devices require efficient power delivery and bidirectional communication.
• Existing solutions face challenges in integrating power recovery and high-speed data transfer.
• Subcutaneous leads for neural interfaces necessitate robust and miniaturized interface electronics.

Purpose of the Study:

• To develop an on-chip interface for simultaneous power recovery and full-duplex communication in active implantable devices.
• To enable bidirectional neural interfacing between brain and chest implants.
• To achieve higher uplink data rates for brain implants compared to downlink.

Main Methods:

• Designed and integrated an on-chip interface within optrode ASICs for AC-coupled 4-wire communication.
• Utilized Manchester encoding for fully-differential, full-duplex data transmission.
• Implemented on-chip power management for regulated and unregulated voltage supplies.
• Fabricated the 4-wire ASIC using 0.35-[Formula: see text] CMOS technology.

Main Results:

• Achieved a head-to-chest uplink data rate of up to 1.6 Mbps and a chest-to-head downlink of 100 kbps.
• Demonstrated on-chip power management providing up to 2.5-mA output current and regulated voltages with 60-dB PSRR.
• The 1.5-mm² ASIC achieved up to 66% power transmission efficiency from chest to brain implant.
• Successfully tested uplink and downlink communication through a 4-wire implantable lead.

Conclusions:

• The developed on-chip interface effectively supports power recovery and full-duplex communication for active implantable devices.
• The system enables higher uplink data rates crucial for advanced neural recording and stimulation.
• This technology advances the development of sophisticated bidirectional neural interfaces.