CMOS-Integrated Low-Noise Junction Field-Effect Transistors for Bioelectronic Applications

Area of Science:

• Integrated circuit design
• Semiconductor device physics
• Bioelectronics

Background:

• Flicker noise in electronic devices is a significant challenge, particularly in sensitive applications like bioelectronics.
• Conventional n-channel MOS devices suffer from high input-referred noise due to oxide interfaces.
• Reducing noise in integrated circuits is crucial for improving signal-to-noise ratio and device performance.

Purpose of the Study:

• To develop and characterize a low-noise junction field-effect transistor (JFET) integrated within a standard CMOS process.
• To demonstrate the noise reduction capabilities of these novel JFETs compared to traditional MOS devices.
• To evaluate the impact of JFET integration on the noise performance of CMOS operational amplifiers.

Main Methods:

• Fabrication of JFETs using a standard 0.18 µm CMOS process.
• Characterization of JFET performance, focusing on input-referred flicker noise.
• Comparison of noise performance between JFETs and equally sized n-channel MOS devices.
• Integration of JFETs into the input stage of CMOS operational amplifiers and subsequent noise analysis.

Main Results:

• The developed CMOS-integrated JFETs exhibit over a factor of 10 reduction in input-referred flicker noise power compared to n-channel MOS devices.
• Elimination of oxide interfaces in contact with the JFET channel is key to the observed noise reduction.
• Integration of JFETs at the input of CMOS operational amplifiers resulted in a factor of 10 reduction in input-referred noise.

Conclusions:

• CMOS-integrated JFETs offer a significant advancement in low-noise electronic device design.
• The elimination of critical oxide interfaces leads to superior noise performance.
• These low-noise JFETs are highly promising for improving the performance of integrated circuits in bioelectronics and other noise-sensitive applications.