Partial Contact Etching and Gate Lowering on Tunneling Field Effect Transistor for Performance and Power Enhancement

In this paper, it is shown that MOL capacitance reduction is one of the major performance boosting knobs for the tunneling field effect transistor (TFET) used for logic application. Low driving current is the weakness of TFET in terms of switching speed, however it can gain advantage fully from reducing MOL capacitance owing to negligible impact of MOL resistance degradation. We have proposed partial contact etching and gate height lowering to reduce MOL capacitance. As a result, 7.3% of delay improvement and 9.0% of reduced energy consumption is achieved with optimized MOL structure.