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III-V Integration on Si(100): Vertical Nanospades
Lucas Güniat1, Sara Martí-Sánchez2, Oscar Garcia3
1Laboratoire des Matériaux Semiconducteurs , École Polytechnique Fédérale de Lausanne , 1015 Lausanne , Switzerland.
Researchers developed novel GaAs nanospades on Si(100) using a unique catalyst pinning method. These defect-free nanostructures show promise for optoelectronics integration on silicon platforms.
Area of Science:
- Semiconductor Nanostructures
- Materials Science
- Nanotechnology
Background:
- Integrating III-V semiconductors with Si(100) is difficult.
- Controlled vertical nanowire growth on Si(100) remains an unsolved challenge.
Purpose of the Study:
- To demonstrate a novel method for growing vertical III-V nanostructures on Si(100).
- To characterize the structure, growth mechanism, and optical properties of these nanostructures.
Main Methods:
- Utilized nonconventional droplet catalyst pinning on ultrathin Si pillars with oxide envelopes.
- Employed a modified growth process enabling contact angle engineering.
- Analyzed nanostructure formation using a growth model based on pentagonal twinning.
Main Results:
- Successfully grew atypical GaAs vertical nanostructures, termed nanospades, on Si(100).
- Achieved virtually defect-free bicrystalline nanospades.
- Identified pentagonal twinning as the key event in nanospade formation.
- Observed optical properties consistent with high crystal purity.
Conclusions:
- The developed nanospade structures are viable for optoelectronics integration on Si(100).
- This method overcomes previous limitations in vertical III-V nanowire growth on silicon.
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