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Published on: February 6, 2014
Speed and energy optimized quasi-delay-insensitive block carry lookahead adder
P Balasubramanian1, D L Maskell1, N E Mastorakis2
1School of Computer Science and Engineering, Nanyang Technological University, Singapore.
A new asynchronous quasi-delay-insensitive (QDI) block carry lookahead adder with redundant carry (BCLARC) offers improved speed and energy efficiency. This novel design outperforms existing asynchronous adders across various architectures, demonstrating significant reductions in cycle time and power-cycle time product.
Area of Science:
- Computer Engineering
- VLSI Design
- Digital Circuits
Background:
- Asynchronous circuits offer potential advantages in speed and power efficiency over synchronous designs.
- Existing asynchronous adders, including QDI and relative-timed variants, present trade-offs in performance and energy consumption.
- Block Carry Lookahead Adders (BCLARC) are known for their efficiency in arithmetic operations.
Purpose of the Study:
- To introduce a novel asynchronous quasi-delay-insensitive (QDI) Block Carry Lookahead Adder with Redundant Carry (BCLARC).
- To evaluate the performance and energy efficiency of the proposed QDI BCLARC against existing asynchronous adder architectures.
- To demonstrate the advantages of the new design in terms of cycle time (CT) and power-cycle time product (PCTP).
Main Methods:
- Implementation of a new asynchronous QDI BCLARC using delay-insensitive dual-rail data encoding.
- Utilization of 4-phase return-to-zero (RTZ) and 4-phase return-to-one (RTO) handshaking protocols.
- Performance and energy efficiency comparison with various asynchronous adders (RCA, CCLA, CSLA, BCLARC, hybrid BCLARC-RCA) using 32/28nm CMOS technology.
Main Results:
- The proposed QDI BCLARC demonstrates significant reductions in Cycle Time (CT) and Power-Cycle Time Product (PCTP) compared to existing asynchronous adders.
- Achieved average reductions of 20.5% in CT and 19.6% in PCTP versus QDI early output RCA.
- Showcased substantial improvements over CCLA (47.5% CT, 47.2% PCTP) and CSLA (32.9% CT, 35.9% PCTP).
Conclusions:
- The developed asynchronous QDI BCLARC offers superior speed and energy efficiency compared to current asynchronous adder designs.
- The novel architecture effectively reduces both data processing time and power consumption, leading to enhanced overall performance.
- This design represents a significant advancement in high-performance, low-power asynchronous adder technology for VLSI applications.
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