Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

Area of Science:

• Digital integrated circuit design
• Computer arithmetic
• Asynchronous circuit design

Background:

• Multiplication is crucial for micro-processing and digital signal processing.
• Quantized Data Independent (QDI) asynchronous array multipliers use specific handshaking protocols (RTZ and RTO).
• Existing QDI multipliers face limitations in efficiency and performance metrics.

Purpose of the Study:

• To design a novel asynchronous partial product generator.
• To design a novel asynchronous half adder.
• To evaluate the efficiency of these new components in QDI array multipliers.

Main Methods:

• Design and integration of a new asynchronous partial product generator.
• Design and integration of a new asynchronous half adder.
• Analysis of QDI array multipliers using the new components and an indicating full adder.

Main Results:

• Significant reductions in cycle time, area, and power consumption compared to existing QDI array multipliers.
• Reductions of up to 17% in cycle time, 16.1% in area, and 15.3% in power with RTZ handshaking.
• Reductions of up to 13% in cycle time, 16.1% in area, and 15.2% in power with RTO handshaking.
• Return-to-One (RTO) handshaking offers slightly better optimization than Return-to-Zero (RTZ).

Conclusions:

• The proposed asynchronous partial product generator and half adder efficiently realize QDI array multipliers.
• The new designs lead to substantial improvements in key design metrics.
• The developed QDI array multipliers were implemented using 32/28nm CMOS technology.