Top-down GaN nanowire transistors with nearly zero gate hysteresis for parallel vertical electronics

Area of Science:

• Materials Science
• Nanotechnology
• Electrical Engineering

Background:

• Vertical gallium nitride nanowire (GaN NW) field-effect transistors (FETs) are explored for advanced electronic applications.
• The feasibility of a 3D vertical architecture for massively parallel electronic integration, particularly for logic circuitry and metrological applications, needs further investigation.

Purpose of the Study:

• To perform direct qualitative and quantitative performance comparisons of FETs based on vertical GaN NWs with varying NW numbers and diameters.
• To demonstrate the feasibility of the vertical 3D architecture concept for massively parallel electronic integration.

Main Methods:

• Fabrication of vertically aligned GaN NWs using a top-down approach combining ICP-DRIE and wet chemical etching on MOVPE-based GaN thin films.
• Construction of FETs with an n-p-n GaN layer stack, inverted p-channel, top drain bridging contact, and wrap-around gating.
• Electrical characterization of integrated NWs, including threshold voltage (Vth) and gate hysteresis measurements using Al2O3 as gate dielectric via ALD.

Main Results:

• Achieved a threshold voltage (Vth) of (6.6 ± 0.3) V, suitable for enhancement-mode (E-mode) operation.
• Observed nearly-zero gate hysteresis with a Vth shift (ΔVth) of approximately 0.2 V using Al2O3 gate dielectric.
• Demonstrated upscaling capability from single NW to NW array in terms of produced currents, despite needing further optimization for linearity.

Conclusions:

• The vertical 3D architecture concept is feasible for massively parallel electronic integration using GaN NWs.
• These findings pave the way for innovative large-scale vertical GaN nanoelectronics, bridging the nanoworld to the macroscopic world.