A 65-nm CMOS Lossless Bio-Signal Compression Circuit With 250 FemtoJoule Performance Per Bit.

Area of Science:

• Integrated Circuit Design
• Bio-medical Engineering
• Signal Processing

Background:

• Bio-physiological signal acquisition requires efficient data handling.
• Existing compression methods often demand significant power and silicon resources.
• There is a need for low-power, compact compression solutions for wearable and implantable devices.

Purpose of the Study:

• To implement a bio-physiological signal compression device using a 65 nm CMOS process.
• To evaluate a novel 'xor-log2-sub-band' compression algorithm for its efficiency.
• To achieve state-of-the-art low power consumption and minimal silicon area.

Main Methods:

• Designed and fabricated a 65 nm CMOS integrated circuit.
• Implemented a novel 'xor-log2-sub-band' data compression algorithm.
• Evaluated power consumption and silicon area for various data rates and use-cases.

Main Results:

• Achieved exceptionally low power consumption: as low as 1.2 pJ/sample-bit at 10 kSa/s and 250 fJ/bit at 5 MSa/sec.
• Demonstrated a diminutive circuit area of 155 µm².
• The 'xor-log2-sub-band' algorithm provides modest compression with very low resource cost.

Conclusions:

• The developed integrated circuit offers state-of-the-art performance in terms of compression versus resource cost.
• This approach is highly beneficial for system optimization, especially in power-constrained bio-medical applications.
• The 'simplest useful compression algorithm' design philosophy yields favorable results for power saving.