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MOS Capacitor

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A Metal-Oxide-Semiconductor (MOS) capacitor is a fundamental structure used extensively in semiconductor device technology, particularly in the fabrication of integrated circuits and MOSFETs (metal-oxide-semiconductor field-effect transistors). The MOS capacitor consists of three layers: a metal gate, a dielectric oxide, and a semiconductor substrate.
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Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Scalable Quantum Integrated Circuits on Superconducting Two-Dimensional Electron Gas Platform

Published on: August 2, 2019

Gate Quantum Capacitance Effects in Nanoscale Transistors.

Sujay B Desai^1,2,3, Hossain M Fahad^1,2,3, Theodor Lundberg¹

¹Electrical Engineering and Computer Sciences , University of California, Berkeley , Berkeley , California 94720 , United States.

|September 19, 2019

Summary

This summary is machine-generated.

Quantum capacitance in nanoscale transistors is crucial for performance. Researchers observed room-temperature quantum effects in carbon nanotube-gated transistors, paving the way for advanced electronic devices.

Keywords:

CNT-gated SOI MOSFET Gate quantum capacitance carbon nanotube gate gate charge limited MOSFET gate starvation limited density of states low-dimensional gate

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Area of Science:

Nanotechnology
Solid State Physics
Materials Science

Background:

Transistor gate dimensions are approaching atomic scales.
Limited electronic density of states (DOS) and quantum capacitance (Cq) significantly impact performance.
Understanding these effects is vital for future nanoscale transistor design.

Purpose of the Study:

To demonstrate the impact of gate Cq and gate electrode dimensionality on nanoscale transistor performance.
To experimentally observe and attribute quantum phenomena in novel transistor architectures.
To explore potential applications in advanced transistor designs.

Main Methods:

Analytical electrostatics modeling of nanoscale transistors.
Experimental characterization of single-walled carbon nanotube (CNT)-gated ultrathin silicon-on-insulator (SOI) transistors.
Analysis of transfer characteristics to identify gate quantization features.

Main Results:

Analytical modeling confirmed that gate Cq and dimensionality affect transistor performance.
First experimental observation of room-temperature gate quantization features in CNT-gated SOI transistors.
Observed features are attributed to Van Hove singularities in the 1D DOS of the CNT gate.

Conclusions:

Gate quantum capacitance and dimensionality are critical factors in nanoscale transistor performance.
Room-temperature gate quantization effects were experimentally verified in CNT-gated SOI transistors.
Engineered gate DOS offers potential for developing multilevel transistors.