A 3 mm × 3 mm Fully Integrated Wireless Power Receiver and Neural Interface System-on-Chip

Area of Science:

• Biomedical Engineering
• Electrical Engineering
• Neuroscience

Background:

• Neural recording and stimulation require integrated, miniaturized electronic systems.
• Wireless power transfer is crucial for implantable neural interfaces to avoid percutaneous wires.

Purpose of the Study:

• To develop a fully integrated wireless power receiver system-on-chip (SoC) for electrocortical neural recording and stimulation.
• To enhance the efficiency and signal integrity of wireless power transfer for neural interfaces.

Main Methods:

• Designed an SoC with an embedded 16-channel electrode array and data transceiver.
• Implemented an H-tree power and signal distribution network for RF interference rejection.
• Utilized a multi-mode buck-boost resonant regulating rectifier (B²R³) for efficient power regulation.

Main Results:

• Achieved a high quality factor (up to 11) in the on-chip receiver coil at 144 MHz.
• Demonstrated a wide input dynamic range (>11 dB) and low transient overshoot (<1 mV) with the B²R³ rectifier.
• Attained an overall wireless power transmission system efficiency (WSE) of 3.4% for a 160 μW load at a 10 mm link distance.
• Maintained signal integrity for analog recording and wireless data transmission.

Conclusions:

• The developed neural interface SoC enables efficient wireless power delivery and high-quality neural signal processing.
• This integrated system is a significant advancement for miniaturized, implantable neural recording and stimulation devices.
• The design addresses key challenges in RF interference rejection and power management for neural interfaces.