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A 128-Channel Level-Crossing-Based Neural Digitization and Spike Sorting SoC With Compact Spatiotemporal Feature
IEEE Transactions on Biomedical Circuits and Systems
|July 16, 2026
Summary
This study introduces a novel 128-channel system-on-chip for neural recording and spike sorting. It achieves high accuracy and efficiency with reduced power consumption for advanced neural interfaces.
Area of Science:
- Neuroscience
- Electrical Engineering
- Biomedical Engineering
Background:
- High-density neural interfaces demand power-efficient data acquisition and on-chip processing for real-time closed-loop control.
- Existing systems face challenges integrating level-crossing analog-to-digital converters (LC-ADCs) with large-scale spike sorting.
- Current on-chip spike sorters have limitations in accuracy and efficiency due to reliance on limited features or high-dimensional data.
Purpose of the Study:
- To present a novel 128-channel system-on-chip (SoC) for neural digitization and spike sorting.
- To address limitations in power consumption, accuracy, and hardware cost of existing neural interface technologies.
- To enable scalable and low-power neural interfaces through integrated solutions.
Main Methods:
- Developed a 22-nm FDSOI CMOS SoC featuring a synchronized LC-ADC front-end with pulse-domain spike detection.
- Implemented a spatial spike realignment module to correct for noise-induced electrode misalignment.
- Designed a compact spatiotemporal feature extractor utilizing 8 features for efficient spike sorting.
Main Results:
- Achieved a 15.34% reduction in detection power and 37.96% in area for the LC-ADC front-end compared to NEO-based methods.
- Improved spike sorting accuracy by 6.83% using the spatial spike realignment module.
- Enhanced accuracy by up to 9.18% with the spatiotemporal feature extractor, while reducing hardware cost.
- Demonstrated ultra-low power consumption: 1.2 µW/channel for recording and 1.09 µW/channel for spike sorting.
Conclusions:
- Successfully demonstrated the first large-scale co-integration of a synchronized LC-ADC front-end with hardware-efficient spatiotemporal spike sorting.
- The developed SoC enables scalable and power-efficient neural interfaces for advanced applications.
- This integrated approach overcomes previous limitations, paving the way for next-generation neural recording technologies.
