CMOS computational camera with a two-tap coded exposure image sensor for single-shot spatial-temporal compressive...

Area of Science:

• Computational Imaging
• Electrical Engineering
• Computer Vision

Background:

• Traditional cameras require high frame rates for high-speed imaging, leading to large data volumes.
• Compressive sensing (CS) offers a way to capture signals below the Nyquist rate, but often requires external hardware.
• Existing CS camera designs can be power-intensive and complex.

Purpose of the Study:

• To develop a power-efficient CMOS computational camera with integrated compressive sensing.
• To demonstrate on-chip spatial-temporal coded exposure for high-speed video acquisition.
• To enable reconstruction of high-speed videos from compressed data.

Main Methods:

• A CMOS image sensor with per-pixel programmable charge modulation was designed.
• Each pixel incorporates a two-tap charge modulator and memory cells for exposure coding.
• A proof-of-concept 128x128 pixel sensor was fabricated and tested for spatial-temporal coded exposure.

Main Results:

• The prototype camera achieved per-frame spatial-temporal coded exposure at 10 frames per second.
• High-speed videos were successfully recovered after reconstruction from the compressed data.
• The system demonstrated efficient operation without external optical modulators.

Conclusions:

• The proposed CMOS computational camera offers a power-efficient solution for compressive sensing applications.
• On-chip integration of compressive sensing simplifies hardware and reduces power consumption.
• This approach enables high-speed video recovery with a compact and efficient camera system.