All WSe₂ 1T1R resistive RAM cell for future monolithic 3D embedded memory integration

Area of Science:

• Materials Science
• Electrical Engineering
• Computer Engineering

Background:

• The Von Neumann bottleneck limits computing performance, necessitating 3D monolithic integration of logic and memory.
• Low-temperature processed material systems are crucial for this integration.
• Two-dimensional (2D) materials offer promising electrical properties and low thermal budgets.

Purpose of the Study:

• To demonstrate a low-temperature hybrid co-integration of a 1T1R memory cell using 2D tungsten diselenide (WSe2).
• To enhance the performance of WSe2-based field-effect transistors (FETs) and resistive random-access memory (RRAM).
• To propose a novel device architecture for high-density 3D embedded memory.

Main Methods:

• Fabrication of a hybrid memory cell comprising a surface-functionalized WSe2 p-FET and a solution-processed WSe2 RRAM.
• Utilizing plasma oxidation to achieve low Schottky barrier height and high mobility in the WSe2 p-FET.
• Device-circuit modeling to guide the design of vertically stacked channel FETs.

Main Results:

• Achieved a low Schottky barrier height of 25 meV and mobility of 230 cm^2 V^-1 s^-1 in the WSe2 p-FET, resulting in a 100x performance enhancement.
• The WSe2 RRAM demonstrated a low switching energy of 2.6 pJ per bit.
• Proposed vertically stacked channel FETs for high-density memory cells (<0.01 μm^2).

Conclusions:

• Successfully demonstrated a low-temperature hybrid co-integration of WSe2-based FET and RRAM for memory applications.
• The developed technology offers a significant performance enhancement and low energy consumption for future computing systems.
• This beyond-silicon approach enables 3D embedded memories, addressing the Von Neumann bottleneck.