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Published on: May 13, 2020
Effect of Word-Line Bias on Linearity of Multi-Level Conductance Steps for Multi-Layer Neural Networks Based on NAND
Sung-Tae Lee1, Suhwan Lim1, Nagyong Choi1
1Department of Electrical and Computer Engineering and ISRC (Inter-University Semiconductor Research Center), Seoul National University, Seoul 08826, Korea.
Abstract:
NAND flash memory which is mature technology has great advantage in high density and great storage capacity per chip because cells are connected in series between a bit-line and a source-line. Therefore, NAND flash cell can be used as a synaptic device which is very useful for a high-density synaptic array. In this paper, the effect of the word-line bias on the linearity of multi-level conductance steps of the NAND flash cell is investigated. A 3-layer perceptron network (784×200×10) is trained by a suitable weight update method for NAND flash memory using MNIST data set. The linearity of multi-level conductance steps is improved as the word line bias increases from Vth -0.5 to Vth +1 at a fixed bit-line bias of 0.2 V. As a result, the learning accuracy is improved as the word-line bias increases from Vth -0.5 to Vth+1.
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