Gate insulator stack engineering for fully CMOS-compatible reservoir computing.

Area of Science:

• Materials Science
• Computer Engineering
• Artificial Intelligence

Background:

• The increasing complexity of temporal datasets in AI necessitates advanced computing architectures.
• Reservoir computing offers a promising approach by leveraging short-term memory for data mapping into high-dimensional spaces.

Purpose of the Study:

• To demonstrate the first fully CMOS-compatible reservoir computing system.
• To investigate the use of gate insulator stack engineering for integrated reservoir computing and neuromorphic applications.
• To analyze the impact of bias conditions on reservoir performance.

Main Methods:

• Fabrication of CMOS circuits and Al2O3/Si3N4 (A/N) devices for reservoir and neuron functions on a single wafer.
• Integration of Al2O3/Si3N4/SiO2 (A/N/O) devices as synaptic elements.
• Experimental analysis of reservoir performance under various bias conditions.

Main Results:

• Successful co-integration of CMOS circuits, A/N reservoir/neuron devices, and A/N/O synaptic devices on a single wafer.
• Demonstration of efficient temporal data processing capabilities.
• Achieved a reduction of approximately 53% in network resources with only a ~0.17%p accuracy drop.
• Exhibited robustness to device variations.

Conclusions:

• The developed gate insulator stack engineering enables fully CMOS-compatible reservoir computing.
• The co-integrated system offers significant resource reduction for temporal data processing.
• This approach paves the way for efficient, on-chip neuromorphic computing solutions.