Effects of Recess Depth Under the Gate Area on the V_th-Shift for Fabricating Normally-Off Field Effect Transistors on...

Fabrication of normally-off field effect transistors (FETs) possessed uniform turn-on threshold voltage (V_th) is of special interests. In this work, they were fabricated using dry etching recess techniques under the gate region, with dry etching conditions of extremely low rate. We report how the recess depth under the gate area induced the V_th shift of normally-off FETs on AlGaN/GaN heterostructure, which were fabricated with a 1.5 nm/min etching rate. Chlorine-based inductively coupled plasma (ICP) was applied to perform the etching process for the AlGaN/GaN heterostructure. Devices were fabricated with different recess depths under the gate area, and examined to determine their performances, particularly the dependence of recess time and recess depth on V_th shift. The applied dry etching conditions resulted in a low-damaged and not-rough morphology on the etched surfaces of AlGaN/GaN. Fine controlled and well defined recess depth of the AlGaN/GaN heterostructure under the gate region was achieved with no etch-stop layers. Conventional fabrication processes were applied with the dry etching conditions of extremely low rate to fabricate normally-off MOSFETs of Al₂O₃/AlGaN/GaN. The achieved V_th of +5.64 V was high positive and the leakage current of off-state was measured as ~10^-6 A/mm.