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Memristor-Based Edge Detection for Spike Encoded Pixels.

Daniel J Mannion¹, Adnan Mehonic¹, Wing H Ng¹

¹Department of Electronic and Electrical Engineering, University College London, London, United Kingdom.

Frontiers in Neuroscience

|February 4, 2020

Summary

This summary is machine-generated.

Silicon oxide memristors exhibit analog behavior for scalable edge detection in machine learning. This approach offers comparable performance to existing methods with fewer components.

Keywords:

computer vision edge detection memristor neuromorphic computing spiking neural networks

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Area of Science:

Materials Science
Computer Science
Electrical Engineering

Background:

Memristors are crucial for machine learning and neuromorphic hardware, serving as memory elements and mimicking synaptic/neuronal functions.
Their versatility makes them ideal for advanced computing architectures.

Purpose of the Study:

To demonstrate an analog mode of operation in silicon oxide memristors.
To apply this analog behavior to the computationally intensive task of edge detection.
To present a scalable solution for edge detection using memristor-based potential dividers.

Main Methods:

Observation and experimental validation of analog memristor behavior.
Implementation of a potential divider circuit utilizing this analog mode.
Performance simulation and benchmarking on the BSDS500 dataset.

Main Results:

Successful demonstration of analog operation in silicon oxide memristors.
Experimental confirmation and simulation of the edge detection circuit's functionality.
Achieved a benchmark score of 0.465 on the BSDS500 dataset, comparable to existing memristor-based solutions.
Demonstrated a lower component count compared to other memristor-based edge detection methods.

Conclusions:

Silicon oxide memristors can operate in an analog mode suitable for image processing tasks like edge detection.
The proposed potential divider circuit offers a scalable and efficient solution for edge detection.
This memristor-based approach achieves competitive performance with reduced hardware complexity.