Fully Depleted, Trench-Pinned Photo Gate for CMOS Image Sensor Applications.

Area of Science:

• Semiconductor Device Physics
• Image Sensor Technology
• Materials Science

Background:

• Conventional CMOS image sensors (CIS) face challenges with implantation-induced defects and contamination.
• Existing pixel designs often struggle with efficient photon detection, charge storage, and transfer.

Purpose of the Study:

• To propose and validate a new CIS pixel design concept utilizing a native epitaxial layer.
• To address limitations in photon detection, charge storage, and charge transfer in CIS pixels.
• To improve overall CIS performance compared to conventional designs.

Main Methods:

• A backside illumination (BSI), p-type, 2-µm-pitch pixel was designed.
• The design integrates a vertical pinned photo gate (PPG), buried vertical transfer gate (TG), sidewall capacitive deep trench isolation (CDTI), and backside oxide-nitride-oxide (ONO) stack.
• Pixel fabrication included parameter variations for optimization.

Main Results:

• Achieved a 13,000 h+ full-well capacity with no charge transfer lag.
• Reached 80% quantum efficiency (QE) at 550 nm.
• Demonstrated a dark current of 5 h+/s at 60 °C, a temporal noise floor of 2 h+, and a dynamic range of 75 dB.

Conclusions:

• The proposed native epitaxial layer-based CIS pixel design offers significant performance improvements.
• This novel design effectively tackles implantation-caused defects and contamination issues.
• The enhanced pixel architecture leads to superior quantum efficiency, reduced noise, and increased dynamic range.