Steerable-Discrete-Cosine-Transform (SDCT): Hardware Implementation and Performance Analysis

Area of Science:

• Digital signal processing
• Video compression technologies
• Hardware architecture design

Background:

• The increasing demand for efficient video compression methods is driven by rising frame resolutions.
• The H.265/High Efficiency Video Coding (HEVC) standard is the current state-of-the-art in video coding.
• Existing methods require further improvements in coding efficiency.

Purpose of the Study:

• To propose a novel hardware architecture for the Steerable Discrete Cosine Transform (SDCT).
• To evaluate the performance of the SDCT within the HEVC standard for enhanced video compression.
• To enable support for high-resolution video formats like 8k UHD.

Main Methods:

• Implementation of a hardware architecture for the Steerable Discrete Cosine Transform (SDCT).
• Integration of SDCT capabilities into the High Efficiency Video Coding (HEVC) framework.
• Performance evaluation at high frequencies and throughputs.

Main Results:

• The developed SDCT hardware architecture operates at 188 MHz with a throughput of 3.00 GSample/s.
• The architecture supports 8k UltraHigh Definition (7680 × 4320) video at 60 Hz.
• Preliminary results indicate improved compression ratios when SDCT is embedded in HEVC.

Conclusions:

• The proposed SDCT hardware architecture offers significant advancements in video compression efficiency.
• This architecture effectively supports demanding 8k UHD video requirements within the HEVC standard.
• The SDCT approach demonstrates potential for superior compression performance in future video coding standards.