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FPGA-Based Soft-Core Processors for Image Processing Applications.

Moslem Amiri1, Fahad Manzoor Siddiqui1, Colm Kelly2

  • 11School of Electronics, Electrical Engineering and Computer Science, Queen's University Belfast, Stranmillis Road, Belfast, Northern Ireland UK.

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Summary
This summary is machine-generated.

This study introduces optimized Field-Programmable Gate Array (FPGA)-based soft-core processors for efficient image processing. This approach achieves high performance in surveillance applications while significantly reducing design time and effort.

Keywords:
FPGAsHeterogeneous multi-core architectureImage processing

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Area of Science:

  • Computer Engineering
  • Digital Signal Processing
  • Embedded Systems

Background:

  • Increasing demand for efficient image data processing in security and surveillance.
  • Field-Programmable Gate Arrays (FPGAs) are key but face challenges in design time and verification.
  • Conventional FPGA design is time-consuming and requires extensive verification and debugging.

Purpose of the Study:

  • To propose an optimized FPGA-based soft-core processor approach for efficient image processing.
  • To reduce the design time and effort associated with FPGA implementations.
  • To achieve high-quality performance comparable to dedicated FPGA designs.

Main Methods:

  • Utilizing optimized FPGA-based soft-core processors.
  • Exploiting task and data level parallelism.
  • Developing a streamlined design flow for programming the processor structure.

Main Results:

  • Achieved high performance for image processing tasks.
  • Demonstrated a Histogram of Gradients algorithm implementation at 328 frames per second (fps).
  • Successfully avoided the lengthy design, verification, and debugging cycles of traditional FPGA methods.

Conclusions:

  • Optimized FPGA-based soft-core processors offer a viable solution for efficient image processing in surveillance.
  • This approach balances high performance with reduced design complexity and time.
  • The methodology enables faster development cycles for embedded image processing applications.