Area efficient folded undecimator based ECG detector

Area of Science:

• Biomedical Engineering
• Digital Signal Processing
• Integrated Circuit Design

Background:

• Cardiac pacemakers require efficient Electrocardiogram (ECG) detection systems.
• Existing ECG detectors often face challenges with hardware area and power consumption.

Purpose of the Study:

• To develop an area-efficient, folded wavelet filter-based ECG detector for cardiac pacemakers.
• To reduce silicon area and improve performance of the Generalized Likelihood Ratio Test (GLRT) block.

Main Methods:

• Implemented a modified folded undecimator ECG detector incorporating a Wavelet Filter Bank, QRS complex detector with a Generalized Likelihood Ratio Test (GLRT) block, and noise detector.
• Applied high-level transformation techniques, including folding transformation and Cutset retiming, to the GLRT block for hardware optimization.
• Synthesized the folded GLRT block architecture using an FPGA Zed board (XC7Z010CLG484-1).

Main Results:

• The modified folded ECG detector achieved high performance metrics: 99.95% sensitivity, 99.97% positive prediction, and a Detection Error Rate (DER) of 0.061.
• Demonstrated significant hardware savings compared to conventional structures.
• The synthesized design showed reduced device utilization and power consumption on the FPGA.

Conclusions:

• The proposed folded wavelet filter-based ECG detector offers a compelling solution for area-efficient pacemaker design.
• The applied folding transformation and Cutset retiming effectively minimize hardware requirements.
• The detector meets the stringent performance demands for reliable cardiac monitoring in pacemakers.