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Verifying Random Quantum Circuits with Arbitrary Geometry Using Tensor Network States Algorithm.

Chu Guo1, Youwei Zhao2,3,4, He-Liang Huang2,3,4,5

  • 1Key Laboratory of Low-Dimensional Quantum Structures and Quantum Control of Ministry of Education, Department of Physics and Synergetic Innovation Center for Quantum Effects and Applications, Hunan Normal University, Changsha 410081, China.

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Summary
This summary is machine-generated.

We developed a new algorithm for simulating random quantum circuits on classical computers. This tensor network method significantly speeds up the verification of quantum computations, making it ideal for near-term quantum devices.

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Area of Science:

  • Quantum Computing
  • Computational Physics

Background:

  • Efficient simulation of quantum circuits is crucial for advancing noisy intermediate-scale quantum (NISQ) devices.
  • Classical simulation methods are essential for verifying quantum hardware and algorithms.

Purpose of the Study:

  • To present a novel tensor network states-based algorithm for computing amplitudes of random quantum circuits.
  • To enhance simulation efficiency through advanced compression and contraction path optimization.

Main Methods:

  • Utilized singular value decomposition (SVD) for tensor network compression.
  • Implemented a two-sided circuit evolution algorithm for further compression.
  • Developed a heuristic algorithm for optimal tensor contraction path computation.

Main Results:

  • The algorithm achieves up to 2 orders of magnitude speedup compared to the Schrödinger-Feynman algorithm.
  • Successfully simulated random quantum circuits up to 104 qubits.
  • Demonstrated effectiveness in verifying shallow random quantum circuits on the Sycamore processor.

Conclusions:

  • The proposed tensor network algorithm is a highly efficient tool for simulating random quantum circuits.
  • This method is well-suited for verifying shallow quantum circuits on near-term quantum computers.
  • Advances classical simulation capabilities for quantum device development and validation.