Implementation of a fully implantable middle-ear hearing device chip

Area of Science:

• Biomedical Engineering
• Electrical Engineering
• Signal Processing

Background:

• Growing prevalence of hearing loss necessitates advanced hearing aid solutions.
• Fully implantable middle ear hearing devices (F-IMEHDs) offer a discreet option for sensorineural hearing loss.
• Implantable signal processors require miniaturization and low power consumption.

Purpose of the Study:

• To design and fabricate a compact, low-power signal-processing chip for F-IMEHDs.
• To implement a modified Fast Fourier Transform (FFT) algorithm for efficient signal processing.
• To integrate key components including a 4-channel Wide Dynamic Range Compression (WDRC) and fitting memory.

Main Methods:

• Developed a signal-processing chip using Verilog-HDL and a modified FFT algorithm.
• Incorporated a 64-point FFT for channel separation and a fitting table for gain matching.
• Fabricated the chip using a 0.18 μm CMOS process and verified its performance on a cadaver.

Main Results:

• The designed chip successfully integrated a 4-channel WDRC, fitting memory, communication control, and pulse density modulator.
• The modified FFT algorithm effectively reduced time delay and system complexity.
• Experimental verification on a cadaver confirmed the chip's functional performance.

Conclusions:

• A novel signal-processing chip for F-IMEHDs was successfully designed, fabricated, and verified.
• The implemented modified FFT algorithm enhances the efficiency of hearing aid signal processing.
• This development contributes to the advancement of implantable hearing aid technology.