A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer.

Area of Science:

• Biomedical Engineering
• Integrated Circuit Design
• Neuroscience

Background:

• Neuromodulation systems require numerous channels, limiting per-channel power and area.
• Chopped neural front-ends improve noise and area efficiency but reduce input impedance.
• Existing impedance boosters can cause detrimental charge transfer to electrodes.

Purpose of the Study:

• To propose and validate a voltage buffer with ultra-low time-averaged offset for neural recording front-ends.
• To mitigate unintended charge transfer to electrodes, thereby extending electrode lifespan.
• To maintain high performance in neural recorders despite area constraints.

Main Methods:

• Design of a voltage buffer utilizing periodic reconfiguration to cancel offset.
• Implementation of the buffer in a 180 nm High Voltage CMOS process.
• Experimental validation of offset cancellation and its effect on input impedance boosting.

Main Results:

• Demonstrated mitigation of signal-independent, buffer offset-induced charge transfer.
• Achieved state-of-the-art performance for a neural recorder front-end.
• Measured area: 0.036 mm², input-referred noise: [Formula: see text] (1-200 Hz) and [Formula: see text] (0.2-10 kHz), power: 13.7 μW.

Conclusions:

• The proposed buffer reconfiguration effectively minimizes unintended charge transfer.
• The design enhances neural recorder reliability and electrode longevity.
• The system achieves excellent performance metrics within strict area and power budgets.