High throughput resource efficient reconfigurable interleaver for MIMO WLAN application.

Area of Science:

• Electrical Engineering
• Computer Engineering
• Telecommunications

Background:

• The increasing demand for high-speed wireless broadband necessitates advanced solutions like Multiple-Input-Multiple-Output (MIMO) Wireless Local Area Networks (WLANs).
• The interleaver's address generation circuitry in MIMO WLAN transceivers presents hardware implementation challenges due to the floor function.
• Efficient hardware implementation of the interleaver is crucial for optimizing MIMO WLAN performance.

Purpose of the Study:

• To propose a novel algorithm for efficiently modeling the address generation circuitry of the MIMO WLAN interleaver.
• To eliminate the need for the computationally intensive floor function in hardware implementation.
• To design and implement a complete interleaver hardware structure on a reconfigurable FPGA platform.

Main Methods:

• Developed a novel algorithm with a mathematical foundation to replace the floor function in address generation.
• Designed and modeled the interleaver hardware in VHDL, utilizing embedded memory and DSP blocks on Spartan 6 FPGAs.
• Verified the algorithm's functionality through software simulations (ModelSim) and hardware testing (Zynq 7000 FPGA with VIO and ILA).

Main Results:

• The proposed design achieved a maximum operating frequency improvement of 196.83% compared to conventional methods.
• Power consumption was reduced by a maximum of 74.27%.
• Memory occupancy was reduced by 88.9%, and throughput increased 8.35 times over IEEE 802.11n requirements.

Conclusions:

• The novel algorithm effectively models the MIMO WLAN interleaver address generator, overcoming hardware implementation challenges.
• The FPGA-based implementation demonstrates significant improvements in operating frequency, power consumption, memory usage, and throughput.
• This work provides a superior design for high-speed wireless broadband applications compared to existing techniques.