A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse...

Area of Science:

• Electronic circuit design
• Hardware implementation of Spiking Neural Networks (SNNs)
• Neuromorphic engineering

Background:

• Large-scale Spiking Neural Networks (SNNs) require optimized hardware for mobile and IoT applications.
• Area and power consumption are critical constraints for on-chip SNN implementations.
• Existing digital implementations often face limitations in energy efficiency and sensitivity.

Purpose of the Study:

• To present an area and power-optimized analog CMOS hardware implementation of a large-scale SNN.
• To develop efficient neuron and synaptic circuits for real-time IoT applications.
• To compare the performance of the proposed SNN with a digital implementation.

Main Methods:

• Designed asynchronous neuronal circuits for enhanced energy efficiency and sensitivity.
• Implemented a Binary Exponential Charge Injector (BECI) based synapse circuit for area and power savings.
• Optimized the SNN model for 9x9 pixel input and minimum bit-width weights.
• Fabricated the SNN chip using a 180 nm CMOS process.
• Replicated the SNN in a full digital implementation for comparison.

Main Results:

• The analog SNN chip occupies a 3.6 mm² core area.
• Achieved a classification accuracy of 94.66% on the MNIST dataset.
• The SNN chip consumes an average power of 1.06 mW, which is 20 times lower than the digital version.
• The BECI synapse circuit offers design scalability for higher resolutions.

Conclusions:

• The proposed analog CMOS SNN hardware offers significant advantages in area and power efficiency for real-time IoT applications.
• The asynchronous neuronal and BECI synapse circuits contribute to the overall performance gains.
• This work demonstrates a viable path towards large-scale SNN deployment on mobile devices.